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products and specifications discussed herein ar e subject to change by micron without notice. 256mb, 512mb (x64, dr): 200-pin ddr sdram sodimm features pdf: 09005aef80765fab/source: 09005aef806e1d28 micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x64hd.fm - rev. e 11/08 en 1 ?2004 micron technology, inc. all rights reserved. ddr sdram sodimm mt8vddt3264hd ? 256mb 1 mt8vddt6464hd ? 512mb for component data sheets, refer to micron?s web site: www.micron.com features ? 200-pin, small-outline dual in-line memory module (sodimm) ? fast data transfer rates: pc2100, pc2700, or pc3200 ? 256mb (32 meg x 64), 512mb (64 meg x 64) ?v dd = v dd q = +2.5v (-40b: v dd = v dd q = +2.6v) ?v ddspd = +2.3v to +3.6v ? 2.5v i/o (sstl_2-compatible) ? internal, pipelined double data rate (ddr) architecture; two data accesses per clock cycle ? bidirectional data strobe (dqs) transmitted/ received with data?that is, source-synchronous data capture ? differential clock inputs (ck and ck#) ? multiple internal device banks for concurrent operation ? selectable burst lengths (bl): 2, 4, or 8 ? auto precharge option ? auto refresh and self refresh modes: 7.8125s maximum average periodic refresh interval ? serial presence-det ect (spd) with eeprom ? selectable cas latency (cl) for maximum compatibility ?dual rank ? gold edge contacts figure 1: 200-pin sodimm (mo-224) notes: 1. not recommended for new designs. 2. contact micron for industrial temperature module offerings. options marking ? operating temperature 2 ? commercial (0c t a +70c) none ? industrial (?40c t a +85c) i ?package ? 200-pin dimm (standard) g ? 200-pin dimm (lead-free) y ? memory clock, speed, cas latency ? 5.0ns (200 mhz), 400 mt/s, cl = 3 -40b ? 6.0ns (167 mhz), 333 mt/s, cl = 2.5 -335 ? 7.5ns (133 mhz), 266 mt/s, cl = 2 1 -26a ? 7.5ns (133 mhz), 266 mt/s, cl = 2.5 1 -265 pcb height: 31.75mm (1.25in) notes: 1. the values of t rcd and t rp for -335 modules show 18ns to al ign with industry specifications; actual ddr sdram device specifications are 15ns. table 1: key timing parameters speed grade industry nomenclature data rate (mt/s) t rcd (ns) t rp (ns) t rc (ns) notes cl = 3 cl = 2.5 cl = 2 -40b pc3200 400 333 266 15 15 55 -335 pc2700 ? 333 266 18 18 60 1 -26a pc2100 ? 266 266 20 20 65 -265 pc2100 ? 266 200 20 20 65
pdf: 09005aef80765fab/source: 09005aef806e1d28 micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x64hd.fm - rev. e 11/08 en 2 ?2004 micron technology, inc. all rights reserved. 256mb, 512mb (x64, dr): 200-pin ddr sdram sodimm features notes: 1. data sheets for the base device s can be found on micron?s web site. 2. all part numbers end with a two-place code (not shown) that desi gnates component and pcb revisions. consult factory for curre nt revision codes. example: mt8vddt6464hdy-335f2 . table 2: addressing parameter 256mb 512mb refresh count 8k 8k row address 8k (a0?a12) 8k (a0?a12) device bank address 4 (ba0, ba1) 4 (ba0, ba1) device configuration 256mb (16 meg x 16) 512mb (32 meg x 16) column address 512 (a0?a8) 1k (a0?a9) module rank address 2 (s0#, s1#) 2 (s0#, s1#) table 3: part numbers and timing parameters ? 256mb base device: mt46v16m16, 1 256mb ddr sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) mt8vddt3264hdg-40b__ 256mb 32 meg x 64 3.2 gb/s 5.0ns/400 mt/s 3-3-3 mt8vddt3264hdy-40b__ 256mb 32 meg x 64 3.2 gb/s 5.0ns/400 mt/s 3-3-3 mt8vddt3264hdg-335__ 256mb 32 meg x 64 2.7 gb/s 6.0ns/333 mt/s 2.5-3-3 mt8vddt3264hdy-335__ 256mb 32 meg x 64 2.7 gb/s 6.0ns/333 mt/s 2.5-3-3 mt8vddt3264hdg-26a__ 256mb 32 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt8vddt3264hdg-265__ 256mb 32 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 mt8vddt3264hdy-265__ 256mb 32 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 table 4: part numbers and timing parameters ? 512mb base device: mt46v32m16, 1 512mb ddr sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) mt8vddt6464hdg-40b__ 512mb 64 meg x 64 3.2 gb/s 5.0ns/400 mt/s 3-3-3 mt8vddt6464hdy-40b__ 512mb 64 meg x 64 3.2 gb/s 5.0ns/400 mt/s 3-3-3 mt8vddt6464hdg-335__ 512mb 64 meg x 64 2.7 gb/s 6.0ns/333 mt/s 2.5-3-3 mt8vddt6464hdy-335__ 512mb 64 meg x 64 2.7 gb/s 6.0ns/333 mt/s 2.5-3-3 mt8vddt6464hdg-265__ 512mb 64 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 mt8vddt6464hdy-265__ 512mb 64 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3
pdf: 09005aef80765fab/source: 09005aef806e1d28 micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x64hd.fm - rev. e 11/08 en 3 ?2004 micron technology, inc. all rights reserved. 256mb, 512mb (x64, dr): 200-pin ddr sdram sodimm pin assignments and descriptions pin assignments and descriptions table 5: pin assignments 200-pin sodimm front 200-pin sodimm back pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1v ref 51 v ss 101 a9 151 dq42 2 v ref 52 v ss 102 a8 152 dq46 3v ss 53 dq19 103 v ss 153 dq43 4 v ss 54 dq23 104 v ss 154 dq47 5 dq0 55 dq24 105 a7 155 v dd 6 dq4 56 dq28 106 a6 156 v dd 7dq157v dd 107 a5 157 v dd 8dq558v dd 108 a4 158 ck1# 9v dd 59 dq25 109 a3 159 v ss 10 v dd 60 dq29 110 a2 160 ck1 11 dqs0 61 dqs3 111 a1 161 v ss 12dm062dm3112 a0 162v ss 13 dq2 63 v ss 113 v dd 163 dq48 14 dq6 64 v ss 114 v dd 164 dq52 15 v ss 65 dq26 115 a10 165 dq49 16 v ss 66 dq30 116 ba1 166 dq53 17 dq3 67 dq27 117 ba0 167 v dd 18 dq7 68 dq31 118 ras# 168 v dd 19 dq8 69 v dd 119 we# 169 dqs6 20 dq12 70 v dd 120 cas# 170 dm6 21 v dd 71 nc 121 s0# 171 dq50 22 v dd 72 nc 122 s1# 172 dq54 23 dq9 73 nc 123 nc 173 v ss 24 dq13 74 nc 124 nc 174 v ss 25 dqs1 75 v ss 125 v ss 175 dq51 26 dm1 76 v ss 126 v ss 176 dq55 27 v ss 77 nc 127 dq32 177 dq56 28 v ss 78 nc 128 dq36 178 dq60 29 dq10 79 nc 129 dq33 179 v dd 30 dq14 80 nc 130 dq37 180 v dd 31 dq11 81 v dd 131 v dd 181 dq57 32 dq15 82 v dd 132 v dd 182 dq61 33 v dd 83 nc 133 dqs4 183 dqs7 34 v dd 84 nc 134 dm4 184 dm7 35 ck0 85 nc 135 dq34 185 v ss 36 v dd 86 nc 136 dq38 186 v ss 37 ck0# 87 v ss 137 v ss 187 dq58 38 v ss 88 v ss 138 v ss 188 dq62 39 v ss 89 nc 139 dq35 189 dq59 40 v ss 90 v ss 140 dq39 190 dq63 41 dq16 91 nc 141 dq40 191 v dd 42 dq20 92 v dd 142 dq44 192 v dd 43 dq17 93 v dd 143 v dd 193 sda 44 dq21 94 v dd 144 v dd 194 sa0 45 v dd 95 cke1 145 dq41 195 scl 46 v dd 96 cke0 146 dq45 196 sa1 47 dqs2 97 nc 147 dqs5 197 v ddspd 48 dm2 98 nc 148 dm5 198 sa2 49 dq18 99 a12 149 v ss 199 nc 50 dq22 100 a11 150 v ss 200 nc
pdf: 09005aef80765fab/source: 09005aef806e1d28 micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x64hd.fm - rev. e 11/08 en 4 ?2004 micron technology, inc. all rights reserved. 256mb, 512mb (x64, dr): 200-pin ddr sdram sodimm pin assignments and descriptions table 6: pin descriptions symbol type description a0?a12 input address inputs: provide the row address fo r active commands, and the column address and auto precharge bi t (a10) for read/write commands, to select one location out of the memory array in the respective device bank. a10 sampled during a precharge command determines whether the precharge applies to one device bank (a10 low, device bank selected by ba0 and ba1) or all device banks (a10 high). the addr ess inputs also provide the op-code during a mode register set command. ba0 and ba1 define which mode register (mode register or extended mo de register) is load ed during the load mode register command. ba0, ba1 input bank address: ba0 and ba1 define the device bank to which an active, read, write, or precharge command is being applied. ck0, ck0#, ck1, ck1# input clock: ck and ck# are differential cloc k inputs. all control, command, and address input signals are sa mpled on the crossing of the positive edge of ck and the negative edge of ck#. output da ta (dq and dqs) is referenced to the crossings of ck and ck#. cke0, cke1 input clock enable: cke enables (registered high) and cke disables (registered low) the internal clock, input buffers, and output drivers. dm0?dm7 input input data mask: dm is an input mask signal for write data. input data is masked when dm is sample d high, along with that input data, during a write access. dm is sampled on both edges of dqs. although dm pins are input-only, the dm loading is designed to match that of dq and dqs pins. ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with s#) define the command being entered. s0#, s1# input chip selects: s# enables (registered low) and disables (registered high) the command decoder. sa0?sa2 input presence-detect address inputs: these pins are used to configure the spd eeprom address range on the i 2 c bus. scl input serial clock for spd eeprom: scl is used to synchronize the presence-detect data transfer to and from the module. dq0?dq63 i/o data input/output: data bus. dqs0?dqs7 i/o data strobe: output with read data . edge-aligned with read data. input with write data. center-aligned with write data. used to capture data. sda i/o serial data: sda is a bidirectional pin used to transfer addresses and data into and out of the presence-det ect portion of the module. v dd supply power supply: +2.5v 0.2v (-40b: +2.6v 0.1v). v ddspd supply serial eeprom power supply: +2.3v to +3.6v. v ref supply sstl_2 reference voltage (v dd /2). v ss supply ground. nc ? no connect: these pins are not co nnected on the module.
pdf: 09005aef80765fab/source: 09005aef806e1d28 micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x64hd.fm - rev. e 11/08 en 5 ?2004 micron technology, inc. all rights reserved. 256mb, 512mb (x64, dr): 200-pin ddr sdram sodimm functional block diagram functional block diagram figure 2: functional block diagram u1 cs# s0# cs# s1# cs# ba0?ba1 a0?a12 ras# cas# we# cke0 cke1 ddr sdram ddr sdram ddr sdram ddr sdram ddr sdram ddr sdram rank 0 ddr sdram rank 1 ck0 ck0# ddr sdram u1, u2, u5, u6 a0 sa0 spd eeprom sda a1 sa1 a2 sa2 wp scl u9 v ref v ss v dd dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 udqs udm dq dq dq dq dq dq dq dq ldqs ldm dq dq dq dq dq dq dq dq u5 ldqs ldm udqs udm dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqs0 dm0 dqs1 dm1 dqs2 dm2 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq dq dq dq dq dq dq dq udqs udm cs# dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 ldqs ldm dqs3 dm3 ldqs ldm dq dq dq dq dq dq dq dq u2 u6 udqs udm dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dqs4 dm4 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dqs5 dm5 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dqs6 dm6 dqs7 dm7 ddr sdram ddr sdram ddr sdram spd eeprom u3 cs# cs# udqs udm dq dq dq dq dq dq dq dq ldqs ldm dq dq dq dq dq dq dq dq ldqs ldm udqs udm dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq u4 cs# cs# udqs udm dq dq dq dq dq dq dq dq ldqs ldm dq dq dq dq dq dq dq dq u8 ldqs ldm udqs udm dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq u7 ck2 ck2# ck1 ck1# ddr sdram u3, u4, u7, u8 v ss v ddspd rank 0 = u1?u4 rank 1 = u5?u8
pdf: 09005aef80765fab/source: 09005aef806e1d28 micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x64hd.fm - rev. e 11/08 en 6 ?2004 micron technology, inc. all rights reserved. 256mb, 512mb (x64, dr): 200-pin ddr sdram sodimm general description general description the mt8vddt3264hd and mt8vddt6464hd are high-speed, cmos, dynamic random access 256mb and 512mb memory mo dules organized in a x64 configuration. these modules use ddr sdram devices with four internal banks. ddr sdram modules use a double data rate architecture to achieve high-speed opera- tion. the double data rate architecture is essentially a 2 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for ddr sdram modu les effectively consists of a single 2 n -bit-wide, one-clock-cycle data transfer at the internal dram core and two corre- sponding n -bit-wide, one-half-clock-cycle da ta transfers at the i/o pins. a bidirectional data strobe (dqs) is transmitted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr sdram during reads and by the memory controller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. ddr sdram modules operate from differential clock inputs (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. commands are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. serial presence-d etect operation ddr sdram modules incorporate serial presence-detect. the spd data is stored in a 256-byte eeprom. the first 128 bytes are progra mmed by micron to identify the module type and various ddr sdram organizations and timing parameters. the remaining 128 bytes of storage are available for use by th e customer. system read/write operations between the master (system logic) and the slave eeprom device occur via a standard i 2 c bus using the dimm?s scl (clock) and sda (data) signals, together with sa[2:0], which provide eight unique dimm/eeprom addr esses. write protect (wp) is connected to v ss , permanently disabling hardware write protect.
pdf: 09005aef80765fab/source: 09005aef806e1d28 micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x64hd.fm - rev. e 11/08 en 7 ?2004 micron technology, inc. all rights reserved. 256mb, 512mb (x64, dr): 200-pin ddr sdram sodimm electrical specifications electrical specifications stresses greater than those listed in ta ble 7 may cause perman ent damage to the module. this is a stress rating only, and func tional operation of the module at these or any other conditions outside those indicated on the device data sheet is not implied. exposure to absolute maximum rating cond itions for extended periods may adversely affect reliability. notes: 1. for further information, refer to technical note tn-00-08: ?thermal applications ,? available on micron?s web site. table 7: absolute maximum ratings symbol parameter min max units v dd v dd supply voltage relative to v ss ?1.0 +3.6 v v in , v out voltage on any pin relative to v ss ?0.5 +3.2 v i i input leakage curren t; any input 0v v in v dd ; v ref input 0v v in 1.35v (all other pins not under test = 0v) address inputs, ras#, cas#, we#, ba ?16 +16 a ck, ck#, s#, cke ?8 +8 dm ?4 +4 i oz output leakage current; 0v v out v dd q; dq are disabled dq, dqs ?10 +10 a t a dram ambient operating temperature 1 commercial 0+70c industrial ?40 +85 c
pdf: 09005aef80765fab/source: 09005aef806e1d28 micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x64hd.fm - rev. e 11/08 en 8 ?2004 micron technology, inc. all rights reserved. 256mb, 512mb (x64, dr): 200-pin ddr sdram sodimm electrical specifications dram operating conditions recommended ac operating conditions are given in the ddr component data sheets. component specifications are available on micron?s web site. module speed grades correlate with component speed grades, as shown in table 8. design considerations simulations micron memory modules are designed to op timize signal integr ity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. however, good sign al integrity starts at the system level. micron encourages designers to simulate th e signal characteristics of the system?s memory bus to ensure adequate signal integrity of the entire memory system. power operating voltages are specified at the dram , not at the edge connector of the module. designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. table 8: module and component speed grades ddr components may exceed th e listed module speed grades module speed grade component speed grade -40b -5b -335 -6 -26a -75z -265 -75
pdf: 09005aef80765fab/source: 09005aef806e1d28 micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x64hd.fm - rev. e 11/08 en 9 ?2004 micron technology, inc. all rights reserved. 256mb, 512mb (x64, dr): 200-pin ddr sdram sodimm electrical specifications i dd specifications notes: 1. value calculated as one mo dule rank in this operating condition; all other module ranks are in i dd 2p (cke low) mode. 2. value calculated reflects all module ranks in this operating condition. ta bl e 9 : i dd specifications and conditio ns ? 256mb (die revision k) values are for the mt46v16m16 ddr sdram only an d are computed from values specified in the 256mb (16 meg x 16) component data sheet parameter/condition symbol -40b -335 units operating one device bank active-precharge current: t rc = t rc (min); t ck = t ck (min); dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd 0 1 416 376 ma operating one device bank active-read-precharge current: burst = 4; t rc = t rc (min); t ck = t ck (min); iout = 0ma; address and control inputs changing once per clock cycle i dd 1 1 496 476 ma precharge power-down standby current: all device banks idle; power- down mode; t ck = t ck (min); cke = (low) i dd 2p 2 32 32 ma idle standby current: cs# = high; all device banks idle; t ck = t ck (min); cke = high; address and other control inputs changing once pe r clock cycle; v in =v ref for dq, dqs, and dm i dd 2f 2 400 400 ma active power-down standby current: one device bank active; power- down mode; t ck = t ck (min); cke = low i dd 3p 2 280 240 ma active standby current: cs# = high; cke = high; one device bank active; t rc = t ras (max); t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd 3n 2 480 440 ma operating burst read current: burst = 2; continuous burst reads; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); iout = 0ma i dd 4r 1 736 656 ma operating burst write current: burst = 2; continuous burst writes; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd 4w 1 736 656 ma auto refresh burst current t rfc = t rfc (min) i dd 5 2 1,280 1,280 ma t rfc = 7.8125s i dd 5a 2 48 48 ma self refresh current: cke 0.2v i dd 6 2 32 32 ma operating bank interleave read current: four device bank interleaving reads; (burst = 4) with auto precharge, t rc = t rc (min); t ck = t ck (min); address and control inputs change only during active read or write commands i dd 7 1 1,176 1,096 ma
pdf: 09005aef80765fab/source: 09005aef806e1d28 micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x64hd.fm - rev. e 11/08 en 10 ?2004 micron technology, inc. all rights reserved. 256mb, 512mb (x64, dr): 200-pin ddr sdram sodimm electrical specifications notes: 1. value calculated as one mo dule rank in this operating condition; all other module ranks are in i dd 2p (cke low) mode. 2. value calculated reflects all module ranks in this operating condition. table 10: i dd specifications and conditions ? 256mb (all other die revisons) values are for the mt46v16m16 ddr sdram only an d are computed from values specified in the 256mb (16 meg x 16) component data sheet parameter/condition symbol -40b -335 -26a/ -265 units operating one device bank active-precharge current: t rc = t rc (min); t ck = t ck (min); dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd 0 1 556 516 496 ma operating one device bank active-read-precharge current: burst = 4; t rc = t rc (min); t ck = t ck (min); iout = 0ma; address and control inputs changing once per clock cycle i dd 1 1 756 736 636 ma precharge power-down standby current: all device banks idle; power-down mode; t ck = t ck (min); cke = (low) i dd 2p 2 32 32 32 ma idle standby current: cs# = high; all device banks idle; t ck = t ck (min); cke = high; address and other control inputs changing once per clock cycle; v in = v ref for dq, dm, and dqs i dd 2f 2 480 400 360 ma active power-down standby current: one device bank active; power-down mode; t ck = t ck (min); cke = low i dd 3p 2 320 240 200/ 240 ma active standby current: cs# = high; cke = hi gh; one device bank active; t rc = t ras (max); t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd 3n 2 560 480 400 ma operating burst read current: burst = 2; continuous burst reads; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); iout = 0ma i dd 4r 1 1,056 896 756 ma operating burst write current: burst = 2; continuous burst writes; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd 4w 1 876 796 656 ma auto refresh burst current t rfc = t rfc (min) i dd 5 2 2,080 2,040 1,880/ 1,960 ma t rfc = 7.8125s i dd 5a 2 48 48 48 ma self refresh current: cke 0.2v i dd 6 2 32 32 32 ma operating bank interleave read current: four device bank interleaving reads; (burst = 4) with auto precharge, t rc = t rc (min); t ck = t ck (min); address and control inputs change only during active read or write commands i dd 7 1 2,056 1,776 1,536/ 1,616 ma
pdf: 09005aef80765fab/source: 09005aef806e1d28 micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x64hd.fm - rev. e 11/08 en 11 ?2004 micron technology, inc. all rights reserved. 256mb, 512mb (x64, dr): 200-pin ddr sdram sodimm electrical specifications notes: 1. value calculated as one mo dule rank in this operating condition; all other module ranks are in i dd 2p (cke low) mode. 2. value calculated reflects all module ranks in this operating condition. table 11: i dd specifications and conditions ? 512mb values are for the mt46v32m16 ddr sdram only an d are computed from values specified in the 256mb (32 meg x 16) component data sheet parameter/condition symbol -40b -335 -265 units operating one device bank active-precharge current: t rc = t rc (min); t ck = t ck (min); dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd 0 1 640 540 480 ma operating one device bank active-read-precharge current: burst = 4; t rc = t rc (min); t ck = t ck (min); iout = 0ma; address and control inputs changing once per clock cycle i dd 1 1 800 660 600 ma precharge power-down standby current: all device banks idle; power-down mode; t ck = t ck (min); cke = (low) i dd 2p 2 40 40 40 ma idle standby current: cs# = high; all device banks idle; t ck = t ck (min); cke = high; address and other control inputs changing once per clock cycle; v in = v ref for dq, dm, and dqs i dd 2f 2 440 360 320 ma active power-down standby current: one device bank active; power-down mode; t ck = t ck (min); cke = low i dd 3p 2 360 280 240 ma active standby current: cs# = high; cke = hi gh; one device bank active; t rc = t ras (max); t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd 3n 2 480 400 360 ma operating burst read current: burst = 2; continuous burst reads; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); iout = 0ma i dd 4r 1 860 680 600 ma operating burst write current: burst = 2; continuous burst writes; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd 4w 1 880 800 560 ma auto refresh burst current t rfc = t rfc (min) i dd 5 2 2,760 2,320 2,240 ma t rfc = 7.8125s i dd 5a 2 88 80 80 ma self refresh current: cke 0.2v i dd 6 2 48 40 40 ma operating bank interleave read current: four device bank interleaving reads; (burst = 4) with auto precharge, t rc = t rc (min); t ck = t ck (min); address and control inpu ts change only during active read or write commands i dd 7 1 1,940 1,640 1,420 ma
pdf: 09005aef80765fab/source: 09005aef806e1d28 micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x64hd.fm - rev. e 11/08 en 12 ?2004 micron technology, inc. all rights reserved. 256mb, 512mb (x64, dr): 200-pin ddr sdram sodimm serial presence-detect serial presence-detect notes: 1. to avoid spurious start and stop conditions, a minimum delay is placed between scl = 1 and the falling or rising edge of sda. 2. this parameter is sampled. 3. for a restart condition or following a write cycle. 4. the spd eeprom write cycle time ( t wrc) is the time from a vali d stop condition of a write sequence to the end of the eeprom intern al erase/program cycl e. during the write cycle, the eeprom bus interface circuit is disabled, sda rema ins high due to pull-up resis- tance, and the eeprom does not respond to its slave address. serial presence-detect data for the latest serial presence-detec t data, refer to micron?s spd page: www.micron.com/spd . table 12: serial presence-detec t eeprom dc operating conditions parameter/condition symbol min max units supply voltage v ddspd 2.3 3.6 v input high voltage: logic 1; all inputs v ih v ddspd 0.7 v ddspd + 0.5 v input low voltage: logic 0; all inputs v il ?1.0 v ddspd 0.3 v output low voltage: i out = 3ma v ol ?0.4v input leakage current: v in = gnd to v dd i li ?10a output leakage current: v out = gnd to v dd i lo ?10a standby current: scl = sda = v dd - 0.3v; all other inputs = v ss or v dd i sb ?30a power supply current: scl clock frequency = 100 khz i cc ?2.0ma table 13: serial presence-detec t eeprom ac operating conditions parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.2 0.9 s 1 time the bus must be free before a new transition can start t buf 1.3 ? s data-out hold time t hd:dat 200 ? ns sda fall time t f ? 300 ns 2 sda rise time t r ? 300 ns 2 data-in hold time t hd:di 0 ? s start condition hold time t hd:sta 0.6 ? s clock high period t high 0.6 ? s clock low period t low 1.3 ? s scl clock frequency f scl ? 400 khz data-in setup time t su:dat 100 ? ns start condition setup time t su:sta 0.6 ? s 3 stop condition setup time t su:sto 0.6 ? s write cycle time t wrc ? 5 ms 4
8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified ov er the power supply and temperat ure range set forth herein. alt hough considered final, these specifications are subject to change, as further product development and data characterization sometime s occur. 256mb, 512mb (x64, dr): 200-pin ddr sdram sodimm module dimensions pdf: 09005aef80765fab/source: 09005aef806e1d28 micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x64hd.fm - rev. e 11/08 en 13 ?2004 micron technology, inc. all rights reserved. module dimensions figure 3: 200-pin ddr sodimm notes: 1. all dimensions are in millimeters (i nches); max/min or typical (typ) where noted. 2. the dimensional diagram is fo r reference only. refer to the jedec mo document for addi- tional design dimensions. 3.8 (0.15) max 67.75 (2.667) 67.45 (2.656) 20.0 (0.787) typ 1.8 (0.071) (2x) 0.61 (0.024) typ 0.46 (0.018) typ 2.0 (0.079) r (2x) pin 199 pin 200 pin 2 front view 2.0 (0.079) typ 6.0 (0.236) typ 63.60 (2.504) 1.0 (0.39) typ 31.9 (1.256) 31.6 (1.244) back view 1.1 (0.043) 0.9 (0.035) typ 11.40 (0.45) typ 47.40 (1.87) typ pin 1 u1 u2 u3 u4 u9 u5 u6 u7 u8 4.0 (0.157) typ 15.35 (0.6) typ

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